Emulation systems may comprise hardware components, such as emulation chips and processors, capable of processor-based (e.g., hardware-based) emulation of logic systems, such as integrated circuits (ICs), application specific integrated circuits (ASICs), central processing units (CPUs), graphics processing units (GPU), field-programmable gate arrays (FPGAs), and the like. By executing various forms of programmable logic, the emulation chips may be programmed to mimic the functionality of nearly any logic system design that is undergoing testing and verification. In other words, emulation systems may be used for a functional verification of the logic system design. Processor-based emulation allows logic designers to prototype a logic system design, before a manufacturer expends resources manufacturing a logic system product based on the logic system design. An emulation system may receive a logic system design in a hardware description language (HDL), such as Verilog or VHDL. In the alternative or in addition, the emulation system may receive the logic system design in a proprietary language. The emulation system may also receive a pre-compiled logic system design in a suitable form based on the specification of the emulation system.
In order to debug a logic system design, a user may have to check various design content and design activity during the runtime of emulating the logic system design. For example, a user may have to track the value of a signal in the logic system design, retrieve contents of a memory, and/or check the inputs to and outputs from various portions of the logic system design. Based on these tracked values, the user (or another program) may identify one or more error conditions. In a conventional approach, a logic system designer includes a debugging logic in the logic system design itself. The debugging logic is compiled with the logic system design and loaded in the emulator. This conventional approach of including the debugging logic within the logic system design is time-consuming and highly inefficient. For example, if the debugging logic has to be changed based upon the behavior of the logic system design during the emulation, the user has to go back to the original logic system design, modify the debugging logic, and synthesize, partition, and compile the entire design. Such compilation may take hours, and even days for more complex designs.